The present invention relates to a substrate injection logic (SIL) operator structure of the substrate-fed logic type and a process for its manufacture and more particularly to such a structure and such a manufacturing process which are compatible with the formation on the same integrated circuit wafer of conventional bipolar-type components.
FIG. 1 schematically illustrates an I.sup.2 L logic operator structure (abbreviation of the term Integrated Injection Logic). As is well known, this structure is generally formed on a P-type substrate 1 overlaid with an N-type buried layer 2 and an epitaxial layer 3 also of N-type but with a lower doping level than that of N-type buried layer 2. In the epitaxial layer 3 there are formed at least two distinct P-type zones 4 and 5. Inside P-type zone 5 are formed several N-type zones 6. An injector metalization I is integral with zone 4, a base metalization B is integral with zone 5 and collector metalizations C.sub.1, C.sub.2 . . . are integral with zones 6. An emitter metalization E is integral with N-type layer 3 or, as is shown, with high-doping-level N-type zones joining the buried layer 2. As is known, this structure is equivalent to the association of a first NPN logic transistor 10 and a second injector transistor 11. FIG. 1 shows which layers form the emitter, the base and the collector of each of these transistors 10 and 11.
Among the numerous advantages of the I.sup.2 L technology, a significant advantage is that it is compatible with conventional technology for construction of bipolar transistors. Thus, there may be formed on the same P-type substrate 1, provided with adjacent highly doped buried layers 2 localized or not and with an epitaxial layer 3 with lower doping level, in separate positions on the same integrated circuit wafer, conventional bipolar transistors and I.sup.2 L logic circuits.
FIG. 2 shows an alternative structure for an I.sup.2 L type logic circuit in which the injection takes place through the substrate. This technology is currently designated in the art by the initials SFL (abbreviation of the term Substrate Fed Logic). In FIG. 2, the same reference numerals as in FIG. 1 have been used where possible to designate identical or corresponding layers. The main difference between the structures of FIGS. 1 and 2 is that the injector transistor 11 is vertical instead of being lateral. Its emitter instead of being formed by a layer 4 formed in the surface of the N-type epitaxial layer 3 is now formed by the P-type substrate 1. This SFL technology has an advantage with respect to the conventional I.sup.2 L technology. This advantage is the capability of greater miniaturization since zone 4 which must be formed on the surface of the conventional I.sup.2 L structure (FIG. 1) as well as the N-type zone separating zone 4 from zone 5 are not required in the SFL structure (FIG. 2).
Nevertheless, this SFL technology has not been used in many practical applications because of the significant technological difficulties in putting in into practice. Consider the N-type zone (including layers 2 and 3) separating the P-type substrate 1 from P-type layer 5. This zone must have both a relatively high doping level in the vicinity of the substrate 1 and a relatively low doping level in the vicinity of its interface with layer 5. Furthermore, the P-type substrate layer 1 at the interface with the N-type zone (layers 2 and 3) must have a high doping level. This has led to the use in the art of heavily doped (more than 5.times.10.sup.18 at/cm.sup.3) P-type substrates. This use of P-type substrates with a high doping level has a significant disadvantage. It is difficult to dope the front face of the substrate because of the self-doping parasite phenomena related to exo-diffusions from the rear face. It is also difficult to make the SFL technology compatible with the technology for manufacturing conventional bipolar transistors which uses relatively low-doped substrates (of the order of 10.sup.15 at/cm.sup.3) rather than the high-doped substrate.
There have been different attempts in the prior art to form structures of the type shown in FIG. 2. There are those which included forming layer 2 from a layer buried in a P.sup.+ -type substrate, then forming N-type layer 3 and P-type layers 5 by successive epitaxies. Another attempt included forming N-type layers 2 and 3 by successive epitaxies, then forming P-type layer 5 by localized diffusion. These processes have proven to be very complex, and do not provide entirely satisfactory results and do not ensure compatibility with conventional bipolar technologies. In the present state of the art, it is not possible to form, on an industrial basis, expitaxied layers localized and limited to positions on an integrated circuit chip formed in accordance with SFL technology logic circuits.